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Hardware architecture
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#	Item
361	Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB) Alen Bardizbanyan Chalmers University of Technology Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2012-12-18 12:36:39 Central processing unit Computer architecture Whitespace CPU cache Cache Tab key C Memory hierarchy Translation lookaside buffer Computer memory Computing Computer hardware
362	Kalray Accelerated Computing v2 Add to Reading List Source URL: anciens-amis-cnrs.com Language: English - Date: 2015-05-27 09:27:22 Graphics hardware Parallel computing Electronics Computer architecture Video cards Graphics processing unit Massively parallel processor array CUDA OpenCL GPGPU Computing Computer hardware
363	Microsoft Word - dlp-vlog-ds-v12.doc Add to Reading List Source URL: www.ftdichip.com Language: English - Date: 2012-05-14 07:25:04 Microcontrollers Electronics Instruction set architectures Central processing unit USB flash drive Universal Serial Bus Firmware PIC microcontroller Computer hardware Computer architecture Embedded systems
364	RouterBOARD Crossroads The perfect AP/CPE. Everything is built in, yet it is the smallest board that MikroTik has ever made. Faster than most devices in this price range, the RouterBOARD Crossroads has a powerful onboard Add to Reading List Source URL: www.routerboard.sk Language: English - Date: 2009-08-14 19:53:00 Networking hardware Power over Ethernet Technology MIPS architecture DBm Ethernet physical layer Embedded system Measurement Ethernet MikroTik Computing
365	Razor thin. Rocket fast. Choose a 2 in 1 powered by the new Intel® Core™ M processor. Less heat. More power. Add to Reading List Source URL: www.intel.eu Language: English - Date: 2014-09-05 16:50:40 Electronics Intel Multi-channel memory architecture Centrino Intel vPro Computer hardware Computing Intel Corporation
366	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2007-09-14 13:31:04 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
367	Dynamic Tunnel Switching for SDN-Based Cellular Core Networks Johanna Heinonen Tapio Partti Marko Kallio (Tieto) Kari Lappalainen (Tieto) Add to Reading List Source URL: conferences.sigcomm.org Language: English - Date: 2014-09-01 23:12:55 Electronics Packet Processing Router Mobility management Network processor Gateway Routing System Architecture Evolution GPRS Tunnelling Protocol Networking hardware Network architecture Computing
368	CS 140: Operating Systems and Systems Programming Midterm Exam Ben Pfaff Stanford University Department of Computer Science July 19, 2005 Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2009-12-29 17:31:12 Virtual memory Computer hardware Pointer Paging C dynamic memory allocation Operating system Preemption Segmentation Ring Memory management Computing Computer architecture
369	A Retrospective on the Dorado, A High-Performance Personal Computer Kenneth A. Pier A Retrospective on the Dorado, A High-Performance Personal Computer Add to Reading List Source URL: www.textfiles.com Language: English - Date: 2008-12-19 13:36:48 Computer engineering Microcode Xerox Alto Instruction set Computer data storage Microarchitecture Memory bandwidth Emulator PDP-10 Computer architecture Computer hardware Central processing unit
370	RB450 The RB450G is a five port Gigabit ethernet router. Comparing to the RB450, the RB450G not only adds Gigabit speed capability, but also 256Mb of RAM, a faster CPU and a microSD card slot for file storage. The device Add to Reading List Source URL: i.mt.lv Language: English - Date: 2014-04-19 00:42:03 Networking hardware Computing Electric power Power over Ethernet Gigabit Ethernet Ethernet over twisted pair Flash memory Network architecture Ethernet IEEE standards Computer hardware

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